The present invention relates to semiconductor device fabrication, more particularly to techniques for via level processing of organosilicate glass (OSG) based interlevel dielectric (ILD) materials and, more particularly, to techniques for removing polymer residue associated with via processing, particularly in a damascene process.
An integrated circuit (IC) device (also referred to as a semiconductor chip) can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of circuit elements are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect) structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors and other circuit elements on a complex IC.
Damascene Techniques
Generally, damascene techniques involve depositing an interlevel dielectric (ILD) layer, such as silicon dioxide (SiO2; also referred to simply as “oxide”), forming an opening in the ILD, overfilling the opening with a metal such as copper (Cu), and removing excess metal using chemical mechanical polishing (CMP), resulting in a planarized interconnect structure. This results in a single “wiring level” or “interconnect level” of an overall “interconnect structure” having many wiring levels. The opening in the interconnect level may be a trench running essentially parallel to the surface of the integrated circuit (IC) chip, and a filled trench is referred to as a “wire” or a “line”. A wire is used to route signals from a first location on the wafer to a second location remote from the first location. The trench for forming the wire may extend only partially (e.g., halfway) into the thickness of the ILD, from the top surface thereof.
Alternatively, an opening in the interconnect level may be a via, extending perpendicular to the surface of IC completely through the ILD for connecting an overlying wire of a higher wiring level or of the present wiring level (in dual damascene, described below) to an underlying wire of a lower wiring level. A filled via is typically simply referred to as a “via”, and sometimes as a “plug” particularly when connecting to an underlying first metallization (M1) or to an element of an underlying MOS (metal oxide semiconductor) structure. Vias and wires are both referred to herein as “conductors”, since their raison d'etre is conducting electrical signals.
In “dual” damascene techniques, the opening in the ILD comprises a lower contact or via hole portion in communication with an upper trench portion, and both the via and the trench portions are simultaneously filled. There are three main sequences (via-first, trench-first, buried-via) for forming dual-damascene differing in the sequence in which the via and trench are patterned and etched, but the resulting structure is generally the same for all three.
Presently, interconnect structures formed on an integrated circuit chip consist of at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size for the current generation of CMOS technology (currently approximately 180 nm (nanometers) designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). A typical width for a via is about 140 nm, and it is common to have redundant vias effecting connections between overlying and underlying wires.
Copper (Cu) and Cu alloys have received considerable attention as a candidate for replacing aluminum (Al) and Al alloys in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistivity than Al. In addition, Cu has improved electrical properties vis-a-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. As used herein, “Cu” is intended to encompass high purity elemental copper as well as Cu-based alloys, such as Cu alloys containing minor amounts of tin, zinc, maganese, titanium, magnesium and germanium.
Due to Cu diffusion through interdielectric layer (ILD) materials, such as silicon dioxide, Cu interconnect structures should be encapsulated by a diffusion “barrier layer” (or “liner”). Conventional practices comprise forming  a damascene opening in an ILD, and depositing a barrier layer such as TaN, lining the sidewalls and bottom of the opening in the ILD prior to depositing the Cu for the via or wire. Typical diffusion barrier layer metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti—TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and a deilicon nitride for encapsulating Cu. The advantage of using such barrier layer materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces between the Cu and other metals as well.
The upper surface of any Cu conductor (typically a wire, since a via, by definition, will always be in contact with a bottom surface of an overlying conductor) must also be protected, such as against oxidation. To cap the upper surface of the copper interconnection, a “capping layer” (or “cap layer”), of a dielectric material such as silicon nitride (Si3N4; also simply referred to as “nitride”, or SiN) is typically employed. The capping layer is also referred to as a “passivation layer”, and is also sometimes referred to as a “barrier layer”. Often the passivation layer must also function as an etch stop layer during subsequent processing, however materials which perform best as etch stop layers typically do not perform best as passivation layers. Silicon oxynitride, SiON, is usually preferred as a etch stop layer but is less desirable as a passivation layer because of delamination which can occur between copper and silicon oxynitride. Silicon nitride, SiN, avoids the delamination problem, and is a preferred passivation material, but is less desirable as an etch stop layer. Further, for Cu/low-k interconnect structures, SiN is essentially a high-k material (k˜7.0). For this reason, various permutations of SiC such as SiCN or SiCNH are preferred (k˜5.2) for the passivation layer for 90 nm and beyond BEOL (back end of line) technologies. (Low-k dielectric materials are discussed below.)
FIG. 1 illustrates a conventional BEOL (back end of line) interconnect structure 100 utilizing copper metallization, the barrier layers and the protective cap/passivation layers described above. The illustrated interconnect structure 100 comprises a first interconnect level 110 and a second interconnect level 130 and is shown (by way of example) as being formed on a substrate 102 such as a semiconductor wafer comprising a plurality of logic circuit elements such as transistors. A single “generic” contact area 104 is illustrated in the substrate 102 and is, for example, an electrode formed on a source or drain region of a MOSFET (metal oxide semiconductor, field effect transistor).
It should clearly be understood that FIG. 1 illustrates but an extremely small (microscopic) portion of an integrated circuit (IC) device, let alone a semiconductor wafer comprising a very large number of such devices. For example, what is shown may have a width of only a few microns (μm) of a semiconductor wafer having a diameter of several inches. Also, in “real life” things are not so neat and clean, rectilinear and uniform as shown. However, for one of ordinary skill in the art to which the invention most nearly pertains, this and other figures presented in this patent application will be highly informative, when taken in context of the associated descriptive text.
The first interconnect level 110 comprises an interlevel dielectric layer (ILD) 112, such as oxide or low-k SiCOH type material which is deposited by a PECVD (plasma enhanced chemical vapor deposition) type process and having an exemplary thickness of approximately 490 nm (nanometers). A trench 114 is formed extending into the ILD 112 from the top (as viewed) surface thereof, such as by a plasma etching type process and having a depth of approximately 275 nm. A via 116 is then formed such as by a plasma etching type process and extending from a selected location at the bottom (as viewed) of the trench 114 to the bottom surface of the ILD 112 (in this case, to the electrode 104 on the underlying substrate 102). The trench 114 and via 116 comprise an “opening” in the ILD 112. A barrier layer 118, such as TaN, is deposited such as by physical vapor deposition (PVD) or chemical vapor deposition (CVD) so that it lines the sidewalls and bottom of the opening in the ILD 112. A typical thickness for the barrier layer 118 is 20 nm and metal for the barrier layer will also deposit on the top surface of the ILD 112. Copper (Cu) 120 is then deposited into the lined opening, and will overfill the opening. Next, chemical mechanical polishing (CMP) is performed to remove excess barrier material and copper from the surface of the ILD 112, leaving a planarized top surface for subsequent semiconductor fabrication processes to be performed. The copper 120 forms a wire (or line) in the trench 114 and a plug (or via) in the via 116. The copper conductor is embedded in the surface of the ILD 112, but because the top surface of the wire is exposed, a capping (or “cap”, or “passivation”) layer 122 such as nitride or SiC is deposited, such as by PECVD (plasma enhanced CVD) on the surface of the wire, and has an exemplary thickness of 35 nm.
The second interconnect level 130 is formed atop (overlying) the first interconnect level 110 and is essentially identical to the first interconnect level 110. Both levels 110 and 130 are shown as being formed by a dual damascene process. The second interconnect level 130 comprises an interlevel dielectric layer (ILD) 112, such as oxide. A trench 114 is formed in the ILD 132. A via 136 is then formed, extending to the bottom surface of the ILD 132. The trench 134 and via 136 comprise the “opening” in the ILD 132. In this case, the via 136 is aligned with the opening 124 in the cap layer 122 of the first interconnect level 110 so that metal filling the via 136 of the second interconnect level 130 can make electrical contact with metal filling the trench 114 of the underlying, first interconnect level 110. The via 136 is typically etched, photoresist, photolithography, and using a fluorine-based chemistry, stopping on the underlying passivation layer 122.
A barrier layer 138, such as TaN, is deposited so that it lines the sidewalls and bottom of the opening in the ILD 132, and is processed as described hereinabove. Copper (Cu) 140 is deposited into the lined opening, and is processed as described hereinabove. The copper 140 forms a wire (or line) in the trench 134 and a plug (or via) in the via 136. A capping layer 142 such as nitride is deposited on the surface of the wire. Where necessary, the capping layer 142 is patterned to have an opening (not shown) to allowing a via of a subsequent (higher) wiring level to make contact with the wire in the trench 134.
The dual damascene interconnect structure 100 shown in FIG. 1 is fabricated utilizing conventional damascene processing steps well known to those skilled in the art. Since such techniques are well known and are not critical for understanding the present invention, a detailed discussion of the same is not given herein. It will be understood that various steps and materials have been omitted, for illustrative clarity, such as seed layers, adhesion layers, and the like.
Dielectric layers 112 and 132 may be the same or different insulative inorganic or organic material. Suitable dielectrics include, but are not limited to: SiO2, fluorinated SiO2, Si3N4, polyimides, diamond, diamond-like carbon, silicon polymers, paralyene polymers, fluorinated diamond-like carbon and other like dielectric compounds.
Low-k Dielectric Materials
Semiconductor devices are typically joined together to form useful circuits using interconnect structures comprising conductive materials (e.g., metal lines) such as copper (Cu) or aluminum (Al) and dielectric materials such as silicon dioxide (SiO2). The speed of these interconnect structures can be roughly assumed to be inversely proportional to the product of the line resistance (R), and the capacitance (C) between lines. Line resistance can be reduced (hence, speed increased) by using copper (Cu) instead of aluminum (Al). To further reduce the delay and increase the speed, it is desirable to reduce the capacitance (C). One way in which this can be done by reducing the dielectric constant “k”, of the dielectric material in the interlevel dielectric layers (ILDs). Thus, there is considerable interest in developing “low-k” materials as well as deposition methods for them that are compatible with integrated circuit technology.
A common dielectric material for use in an interlevel dielectric layer (ILD) is silicon dioxide (SiO2, also referred to simply as “oxide”). Oxide has a dielectric constant k of at least 3.85, typically 4.1-4.3, or higher. Air has a dielectric constant k of approximately 1.0. By definition, a vacuum has a dielectric constant k of 1.0.
A variety of low-k dielectric materials are known, and are typically defined as materials having a dielectric constant k less than 3.85, or in other words, less than that of oxide. Sometimes, materials having k<2.5 are referred to as “ultralow-k”. These low-k and ultralow-k dielectric materials can generally be characterized by their composition and/or by the way in which they typically are deposited.
Deposition is a process whereby a film of either electrically insulating (dielectric) or electrically conductive material is deposited on the surface of a semiconductor wafer. Chemical Vapor Deposition (CVD) is used to deposit both dielectric and conductive films via a chemical reaction that occurs between various gases in a reaction chamber. Plasma enhanced Chemical Vapor Deposition (PECVD) uses an inductively coupled plasma to generate different ionic and atomic species during the deposition process. PECVD typically results in a low temperature deposition compared to the corresponding thermal CVD process. Spin-on deposition is used to deposit materials such as photoresist, and can also be used to deposit dielectric materials. A wafer is coated with material in liquid form, then spun at speeds up to 6000 rpm, during which the liquid is uniformly distributed on the surface by centrifugal forces, followed by a low temperature bake which solidifies the material.
Examples of spin-on low-k materials include:
BCB (divinylsiloxane bisbenzocyclobutene), sold by Dow Chemical.
SiLK™, an organic polymer with k=2.65, similar to BCB, sold by Dow Chemical.
NANOGLASS™, an inorganic porous polymer with k=2.2, sold by Honeywell.
FLARE 2.0™ dielectric, an organic low-k poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif.
Inorganic materials such as spin-on glass (SOG), fluorinated silicon glass (FSG) and, particularly, methyl-doped porous silica which is referred to by practitioners of the art as black diamond, or BD.
Organo-silicate materials, such as JSR LKD 5109 (a spin-on material, Japan Synthetic Rubber).
Organic polymers (fluorinated or non-fluorinated), inorganic polymers (nonporous), inorganic-organic hybrids, or porous materials (xerogels or aerogels).
Materials in the parylene family of polymers, the polynapthalene family of polymers, or polytetrafluoroethylene.
Examples of low-k Chemical Vapor Deposition (CVD) and Plasma Enhanced CVD (PECVD) low-k materials include:
Black Diamond™, a organosilicon glass (OSG) which is a Si—O—C—H type of material, with a dielectric constant k of 2.7 to 3.0 (e.g., 2.9), sold by Applied Materials Inc.
CORAL™, also an organosilicon glass (OSG) which is a Si—O—C—H type of material, with k of 2.7-3.0, sold by Novellus Systems, Inc.
fluorinated SiO2 glass, and amorphous C:F.
It is also known that pores in dielectric materials can lower the dielectric constant. Low-k dielectric materials can typically be deposited ab initio either with or without pores, depending on process conditions. Since air has a near 1 dielectric constant, porous films exhibit reduced dielectric constants than the base material in which they are developed. (If the dielectric is not “porous”, it is referred to as being “dense”). Generally, it is the spin-on materials (e.g., SiLK, NANOGLASS) materials that exhibit a high degree of porosity. The PECVD materials generally do not exhibit such high degree of porosity, due to the method of deposition. As a result, it is very difficult to prepare a CVD film with a k value <2.5. For low-k dielectric materials having pores, it is important that an additional layer or film overlies the porous dielectric layer to act as a moisture barrier for the porous dielectric layer.
In one class of interconnect structures, the thinwires are formed in a low dielectric constant (k) organosilicate (e.g., SiCOH) inter-level dielectric (ILD) layer, and the fatwires are made in a silicon dioxide ILD having a dielectric constant of about 4. (Class here refers to the type of low-k material, namely OSG films, as opposed to polymeric films such as SiLK, FLARE and so on.)
One of the many challenges associated with the fabrication of the said thinwires and fatwires for 90 nm and beyond CMOS BEOL technologies is the issue of ash induced consumption of passivation layer material during via level damascene processing.
As mentioned above (ref FIG. 1), the via 136 in the second interconnect level 130 is etched, stopping on the capping layer 122 of the previous interconnect level 110 using normal etching procedures. For oxide based dielectrics, this involves the use of fluorine-based chemistry, which results in fluorine-based polymer byproducts being deposited on the sidewalls of the via, the surface of the wafer and the walls of the reaction chamber. Then, during ashing to remove photoresist (PR) for forming the via 136, the capping layer 122 under the via 136 is compromised because there is fluorine byproduct from polymers formed during etching.
During via level etching of the OSG ILD material, specific fluorine-based chemistries (C4F8 and/or C4F6) are employed to acquire sufficient selectivity to the carbon containing capping layer (SiCH/BLoK or SiCNH/NBLok for example). This, so-called, over etch processing step is typically run for a specified time period to compensate for film and plasma non-uniformities in addition to wafer-to-wafer and chamber-to-chamber variability. In this manner, overetch processes typically have as much as 20% to 30% overetch built into the processing step to ensure minimal contact resistance between via and underlying trench layer.
As will become evident from the descriptions that follow, the present invention is most applicable to any dielectric material, such as OSG low-k ILDs, both dense and porous, the etching of which requires fluorine-based chemistries. On the other hand, organic type ILDs are not etched w/fluorine but rather with any oxidizing or reducing chemistry.
Low-k dielectric films, called BLOk™ (SiC, may have some H, so SiCH) and N-BLoK (SiCNH), have been developed for use in copper damascene processes. These silicon carbide films are deposited using trimethylsilane ((CH3)3SiH) and have a lower dielectric constant (k<5) than that of conventional SiC films (k>7) generated by SiH4 and CH4, and that of plasma silicon nitride (k>7). Characterisation of the film, including physical, electrical, and copper diffusion properties, and etch selectivity, shows that this film is a good cap layer/etch stop for low-k copper damascene applications. Its low dielectric constant enables a significant reduction in the effective k value of the completed dielectric stack in damascene devices.
The use of SiCOH-based materials for 90 nm technology presents many etching challenges: one such challenge occurs during Via-level damascene processing; namely achieving minimal NBLoK (passivation layer) loss post processing. The majority of this passivation layer loss can actually occur during ashing as residual chamber and wafer fluorine is “liberated” during ashing leading to etching of the passivation which if negligible can lead to potential Cu oxidation and consequent reliability issues.
In semiconductor manufacturing, plasma ashing is the process of removing the photoresist from an etched wafer. Using a plasma source, a monatomic reactive specie is generated. Oxygen or fluorine are the most common reactive specie. The reactive specie combines with the photoresist to form ash which is removed with a vacuum pump.
U.S. Pat. No. 6,221,772 discloses a method of in-situ cleaning polymers from holes on a semiconductor wafer and in-situ removing the silicon nitride layer. The semiconductor wafer comprises a substrate, a silicon nitride (Si3N4) layer on the substrate, a silicon oxide (SiO2) layer on the silicon nitride layer, and a photo-resist layer on the silicon oxide layer. The silicon oxide layer and the photo-resist layer have a hole extending down to the silicon nitride layer. The hole contains polymer left after etching of the silicon oxide layer. The method comprises performing a in-situ plasma ashing process by injecting oxygen (O2) and argon (Ar) to completely remove the photo-resist layer and the polymer remaining within the hole. Subsequently, the silicon nitride layer was removed in the same chamber. The flow rate of O2 is maintained between 50˜2000 sccm (standard cubic centimeter per minute) and the flow rate of Ar is maintained between 50˜500 sccm.
U.S. Pat. No. 6,534,415 discloses a method of removing polymer residues after tungsten etch back. A plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.